| Senior
Logic Engineer - TX
The Senior Logic and Verification
Engineer will have hands-on responsibility for RTL
coding and function verification, and eventually will
have responsibility for delivering optimized netlists
for competitive high-speed/low-power CPUs.
There are multiple opportunities
available.
Duties & Resp.
 |
Build/Analyze micro-architecture and
write/modify RTL for high-speed and low power
|
|
Verify functionality through
simulation, debugging and formal equivalence
|
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Analyze critical path and extract
custom blocks / data path blocks for speed
optimization |
|
RTL-to-netlist generation through
synthesis |
|
Perform floorplan/timing analysis
|
Background /Experience Required:
|
MSEE and 7-10 years relevant experience
(or equivalent education and experience) |
|
7+ years of CPU/ASIC design experience
|
|
Hands-on experience with CPU
architecture, microarchitecture, RTL design and
verification with block compositon through synthesis,
floorplanning, and timing closure |
|
Hands-on experience with: Synopsys DC
and Primetime; formal equivalence tools (Formality,
Conformal); function simulation tools (NC-Verilog,
Simvision, VCS, Debussy); and Perl, TCL, Shell, and
other script languages |
Desired
|
Hands-on experience with formal
equivalence tools across multiple cycle boundary
|
Necessary Skills /Attributes Required:
|
Ability to solve problems on logic
design issues |
|
Excellent communication and
interpersonal skills |
|
Ability to clearly and precisely
communicate design changes to colleagues |
|
Ability to work effectively in a
production environment |
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Flexible and adaptable to challenging
schedule |
Desired:
|
Experience working in multi-cultural
environments |
|
|
If you meet the above requirements please send an email to
tstipe@austinprosearch.com. Please include your industry
experience and contact information, or attach your Word
resume. Your information will remain confidential.
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